axhal/platform/x86_pc/
boot.rs

1use core::arch::global_asm;
2
3use x86_64::registers::control::{Cr0Flags, Cr4Flags};
4use x86_64::registers::model_specific::EferFlags;
5
6use axconfig::{TASK_STACK_SIZE, plat::PHYS_VIRT_OFFSET};
7
8/// Flags set in the ’flags’ member of the multiboot header.
9///
10/// (bits 1, 16: memory information, address fields in header)
11const MULTIBOOT_HEADER_FLAGS: usize = 0x0001_0002;
12
13/// The magic field should contain this.
14const MULTIBOOT_HEADER_MAGIC: usize = 0x1BADB002;
15
16/// This should be in EAX.
17pub(super) const MULTIBOOT_BOOTLOADER_MAGIC: usize = 0x2BADB002;
18
19const CR0: u64 = Cr0Flags::PROTECTED_MODE_ENABLE.bits()
20    | Cr0Flags::MONITOR_COPROCESSOR.bits()
21    | Cr0Flags::NUMERIC_ERROR.bits()
22    | Cr0Flags::WRITE_PROTECT.bits()
23    | Cr0Flags::PAGING.bits();
24const CR4: u64 = Cr4Flags::PHYSICAL_ADDRESS_EXTENSION.bits()
25    | Cr4Flags::PAGE_GLOBAL.bits()
26    | if cfg!(feature = "fp_simd") {
27        Cr4Flags::OSFXSR.bits() | Cr4Flags::OSXMMEXCPT_ENABLE.bits()
28    } else {
29        0
30    };
31const EFER: u64 = EferFlags::LONG_MODE_ENABLE.bits() | EferFlags::NO_EXECUTE_ENABLE.bits();
32
33#[unsafe(link_section = ".bss.stack")]
34static mut BOOT_STACK: [u8; TASK_STACK_SIZE] = [0; TASK_STACK_SIZE];
35
36global_asm!(
37    include_str!("multiboot.S"),
38    mb_magic = const MULTIBOOT_BOOTLOADER_MAGIC,
39    mb_hdr_magic = const MULTIBOOT_HEADER_MAGIC,
40    mb_hdr_flags = const MULTIBOOT_HEADER_FLAGS,
41    entry = sym super::rust_entry,
42    entry_secondary = sym super::rust_entry_secondary,
43
44    offset = const PHYS_VIRT_OFFSET,
45    boot_stack_size = const TASK_STACK_SIZE,
46    boot_stack = sym BOOT_STACK,
47
48    cr0 = const CR0,
49    cr4 = const CR4,
50    efer_msr = const x86::msr::IA32_EFER,
51    efer = const EFER,
52);
axhal/platform/x86_pc/boot.rs

axhal/platform/x86_pc/
boot.rs
